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Programmable Synchronous DC/DC Converter, Dual LDO Controller
POWER MANAGEMENT Description
The SC2688 combines a synchronous voltage mode controller with two low-dropout linear regulators providing most of the circuitry necessary to implement three DC/DC converters for powering advanced microprocessors such as Pentium(R) III. The SC2688 switching section features latched drive output for enhanced noise immunity, pulse by pulse current limiting and logic compatible shutdown. The SC2688 switching section operates at a fixed frequency of 140kHz, providing an optimum compromise between size, efficiency and cost in the intended application areas. The SC2688 linear sections are low dropout regulators with short circuit protection, supplying 1.5V for GTL bus and 2.5V for non-GTL I/O.
SC2688
Features
*Synchronous design, enables no heatsink solution 95% efficiency (switching section) Designed for embedded Pentium(R) III requirements 1.5V, 2.5V short circuit protected linear controllers
Applications
Embedded Pentium(R) III microprocessor supplies.
Typical Application Circuit
12V + 5V + 1500uF
x4
47uF
0.1uF
10
11 4
BST VCC LDOEN EN AGND LDOV GATE2 LDOS2
CS+ CSDH DL FB PGND GATE1 LDOS1
7 6 8 10 13 9 1 2
0.1uF 0.1uF 2R2 2R2 1.00k 1.9uH 2.32k VCC_CORE 5mOhm
EN
0.1uF
5 12 16 14 15 3
+
0.1uF
SC2688S 3.3V 1k + 330uF + 330uF 330uF + 1.5V 2.5V 1500uF
x6
Revision: March 25, 2004
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SC2688
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter VCC to AGND PGND to AGND BST to PGND DH to PGND, DL to PGND (Note2) Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec. Thermal Resistance Junction to Ambient Thermal Impedance Junction to Case
Symbol VIN
Maximum -0.3 to +7 1 -0.3 to +15 -1 to +15
Units V V V V C C C C C/W C/W
TA TJ TSTG TLEAD J A J C
0 to +70 0 to +125 -65 to +150 300 80 25
Electrical Characteristics
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; TA = 0 to 70C
Parameter Switching Section Output Voltage Supply Voltage Supply Current Load Regulation Line Regulation Current Limit Voltage Oscillator Frequency Oscillator Max Duty Cycle Peak DH Sink/Source Current Peak DL Sink/Source Current Gain (AOL) FB Input current Dead Time
Conditions
Min
Typ
Max
Units
IO = 2A in Application Circuit VCC VCC = 5.0V IO = 0.8A to 15A
1.238 4.5
1.250
1.263 7
V V mA % %
8 1 0.5 60 120 90 70 140 95
15
85 160
mV kHz % A mA A mA
BSTH - DH = 4.5V, DH- PGNDH = 3.3V DH- PGNDH = 1.5V BSTL - DL = 4.5V, DL - PGNDL= 3.3V DL- PGNDH = 1.5V VOSENSE to VO VFB = 1.25V
1 100 1 100 35 1 40 100 2
dB uA ns
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SC2688
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; TA = 0 to 70C
Parameter Linear Sections Quiescent Current Output Voltage LDO1 Output Voltage LDO2 Reference Voltage Gain (AOL) Load Regulation Line Regulation Output Impedance LDOV Undervoltage Lockout LDOEN Threshold LDOEN Sink Current Overcurrent Trip Voltage Power-up Output Short Circuit Immunity Output Short Circuit Glitch Immunity Gate Pulldown Impedance VOSENSE Impedance
Conditions
Min
Typ
Max
Units
LDOV = 12V 2.493 1.496 Iref < 100uA LDOS (1,2) to GATE (1,2) IO = 0 to 8A 1.246 2.525 1.515 1.265 90
5 2.556 1.534 1.284
mA V V V dB
0.3 0.3
% % k V V A A % ms ms k k
VGATE = 6.5V 6.5 1.3 LDOEN = 3.3V LDOEN = 0V % of Vo set point 20 1 0.5 GATE (1,2) -AGND; VCC+BST=0V 80 10
1 8.0
1.5 10 1.9
0.01 -200 40 5 4 300
1.0 -300 60 60 30 750
Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) See Gate Resistor Selection recomendations.
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SC2688
POWER MANAGEMENT Pin Configuration
TOP VIEW
GATE1 LDOS1 LDOS2 VCC LDOEN CSCS+ DH 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AGND GATE2 LDOV FB EN BST DL PGND
Ordering Information
Device
(1)
P ackag e SO-16
Linear Voltage 1.5V/2.5V
Temp Range (TJ) 0 to 125C
SC2688STR
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices.
(16 Pin SOIC)
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name GATE1 LDOS1 LDOS2 VCC LDOEN CSCS+ DH PGND DL BST EN (1) FB LDOV GATE2 AGND Gate Drive Output LDO1 Sense Input for LDO1 Sense Input for LDO2 Input Voltage LDO Supply Monitor. Current Sense Input (negative) Current Sense Input (positive) High Side Driver Output Power Ground Low Side Driver Output Supply for Drivers Logic low shuts down the converter, High or open for normal operation Switcher section feedback input +12V for LDO section Gate Drive Output LDO2 Small Signal Analog and Digital Ground Pin Function
Note: (1) All logic level inputs and outputs are open collector TTL compatible.
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SC2688
POWER MANAGEMENT Block Diagram
VCC CSCS+ EN
CURRENT LIMIT REF
70mV
+ LEVEL SHIFT AND HIGH SIDE DRIVE
BST
+
DH
FB
-
ERROR AMP +
AGND
OSCILLATOR R Q S 1.265V REF
SHOOT-THRU CONTROL
LDOEN LDOS1 GATE1
2.5V FET CONTROLLER 1.5V FET CONTROLLER SYNCHRONOUS MOSFET DRIVE
DL
PGND LDOV GATE2 LDOS2
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SC2688
POWER MANAGEMENT Layout Guidelines
Careful attention to layout requirements are necessary for successful implementation of the SC2688 PWM controller. High currents switching at 140kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency.
12V IN
5V
10
1 2 3 4
0.1uF
GATE1 AGND LDOS1 GATE2 LDOS2 VCC LDOEN CSCS+ DH SC2688 LDOV FB EN BST DL PGND
16 15 14 13 12 11 10 9
Q2 Q1 Cin + L 1.00k
2.32k
5mOhm Vout
5 6 7
0.1uF
Cout
8
3.3V Q3 Cin Lin Cout Lin1
Vo Lin1
Heavy lines indicate high current paths.
Layout Diagram SC2688
Vo Lin2 Q4 Cout Lin2
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SC2688
POWER MANAGEMENT Layout Guidelines (Cont.)
4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC2688 is best placed over a quiet ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. PGND should be returned to the ground plane close to the package. The AGND pin should be connected to the ground side of (one of) the output capacitor(s). If this is not possible, the AGND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 6) Vcc for the SC2688 should be supplied from the 5V supply through a 10 resistor, the Vcc pin should be decoupled directly to AGND by a 0.1F ceramic capacitor, trace lengths should be as short as possible. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces running back to CS+ and CS- on the SC2688 should run parallel and close to each other. The 0.1F capacitor should be mounted as close to the CS+ and CS- pins as possible. 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s).
5V
Currents in Power Section
+ Vout +
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SC2688
POWER MANAGEMENT Component Selection
SWITCHING SECTION OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from:
R ESR Where Vt = Maximum transient voltage excursion It = Transient current step Vt It
and 0% duty cycle capability, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from:
ILRIPPLE = VIN 4 L fOSC
For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10m. To meet this kind of ESR level, there are three available capacitor technologies.
Each Cap. Technology C (F) 330 330 1500 ESR (m) 60 25 44 Total ESR (m) 10 8.3 8.3
Ripple current allowance will define the minimum permitted inductor value. POWER FETS - The FETs are chosen based on several criteria, with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses.
a) Conduction losses are simply calculated as:
2 PCOND = IO RDS(on)
Qty. Rqd. C (F) 6 3 5
Low ESR Tantalum OS-CON Low ESR Aluminum
2000 990 7500
where = duty cycle VO VIN
The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. The maximum inductor value may be calculated from:
L R ESR C VA It
b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then:
PSW = IO VIN 10 -2
or more generally,
PSW = IO VIN ( t r + t f ) fOSC 4
where VA is the lesser of VO or (VIN - VO )
c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be:
PRR = QRR VIN fOSC
The calculated maximum inductor value assumes 100%
To a first order approximation, it is convenient to only con-
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SC2688
POWER MANAGEMENT Component Selection (Cont.)
sider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be: Using 1.5X Room temp RDS(ON) to allow for temperature rise.
FET type IRL34025 IRL2203 Si4410 RDS(on) (m) 15 10.5 20 PD (W) 1.69 1.19 2.26 Package D2Pak D2Pak S0-8
INPUT CAPACITORS - since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size. GATE RESISTOR SELECTION - The gate resistors for the top and bottom switching FETs limit the peak gate current and hence control the transition time. It is important to control the off time transition of the top FET, it should be fast to limit switching losses, but not so fast as to cause excessive phase node oscillation below ground as this can lead to current injection in the IC substrate and erratic behaviour or latchup. The actual value should be determined in the application, with the final layout and FETs. SHORT CIRCUIT PROTECTION - LINEARS The Short circuit feature on the linear controllers is implemented by using the Rds(on) of the FETs. As output current increases, the regulation loop maintains the output voltage by turning the FET on more and more. Eventually, as the Rds(on) limit is reached, the FET will be unably to turn on more fully, and output voltage will start to fall. When the output voltage falls to approximately 40% of nominal, the LDO controller is latched off, setting output voltage to 0. Power must be cycled to reset the latch. To prevent false latching due to capacitor inrush currents or low supply rails, the current limit latch is initially disabled. It is enabled at a preset time (nominally 2ms) after both the LDOV and LDOEN pins rise above their lockout points. To be most effective, the linear FET Rds(on) should not be selected artificially low, the FET should be chosen so that, at maximum required current, it is almost fully turned on. If, for example, a linear supply of 1.5V at 4A is required from a 3.3V 5% rail, max allowable Rds(on) would be. Rds(on)max = (0.95*3.3-1.5)/4 400m To allow for temperature effects 200m would be a suitable room temperature maximum, allowing a peak short circuit current of approximately 15A for a short time before shutdown.
BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by:
2 PCOND = IO RDS( on) (1 - )
For the example above:
FET type IRL34025 IRL2203 Si4410 RDS(on) (m) 15 10.5 20 PD (W) 1.33 0.93 1.77 Package D2Pak D2Pak S0-8
Each of the package types has a characteristic thermal impedance. For the surface mount packages on double sided FR4, 2 oz printed circuit board material, thermal impedances of 40oC/W for the D2PAK and 80oC/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below:
Temperature Rise (OC) FET type IRL34025 IRL2203 Si4410 Top FET 67.6 47.6 180.8 Bottom FET 53.2 37.2 141.6
It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4.
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SC2688
POWER MANAGEMENT Theory of Operation (Linear OCP)
The Linear controllers in the SC2688 have built in Overcurrent Protection (OCP). An overcurrent is assumed to have occured when the external FET is turned fully on and the output currrent is RDS(ON) limited, this is detected by the gate voltage going very high while the output voltage is below approximately 40% of it's setpoint. To allow for capacitor charging and very short overcurrent durations, the gate voltage is ramped very slowly upwards whenever the output voltage is below the OCP threshold. To guarantee that the LDO output voltage is capable of reaching it's setpoint, the gate drive is disabled until both LDOV Undervoltage Lockout (UVLO) and LDOEN Threshold values are exceeded, ensuring that there is sufficient gate drive capability and sufficient LDO input voltage capability. A block diagram of one LDO controller is shown below.
Gate 1.4V/us Vout 1V/ms Vout/2
Time
Startup with no short circuit
12V LDOV LDOEN
3.3V
If at some later time, a short circuit is applied to the output, the GATEx voltage will ramp up quickly as Vout falls to try and maintain regulation. Once Vout has fallen to the OCP threshold, switch S1 will open and the gate will continue ramping at the 1V/ms rate. If the short is not removed before the GATEx output reaches approximately LDOV - 0.7V, the GATEx pin will be latched low, disabling the LDO
Short applied
+ 10pF
C RAMP gm + + VREF 1.26V SWITCH CLOSED ON LOW + 10nA R R1 14uA S1 1.3V -
LDOV
GATEx
R2
1V/ms Gate
LDOV-0.7V
LDOSx
Vout
R
+
Vout Vout/2 Time
AGND
RESET BY LDOV LOW Q
Short circuit after startup
S + R LDOV-0.7V
If the LDO tries to start into a short, the gate ramps at the 1V/ms rate to LDOV - 0.7V, where the GATEx pin will be latched low.
During a normal start-up, once LDOV and LDOEN have reached their thresholds, the GATEx pin is released and CRAMP is charged by 10nA causing the GATEx voltage to ramp at 10nA/10pF = 1V/ms. Once the GATEx output has ramped to the external FET threshold, Vout starts to ramp up, following GATEx. When Vout reaches the OCP threshold, approximately 40% of setpoint, switch S1 is closed and GATEx ramps up at a much faster rate, followed by Vout, until Vout reaches setpoint and the loop settles into steady state regulation.
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Gate
LDOV-0.7V
1V/ms
Time
Startup into short circuit
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SC2688
POWER MANAGEMENT Typical Characteristics
Typical Efficiency (Switching section)
96%
Typical Ripple, Vo=2.0V, Io=10A
PIN Descriptions
92% Efficiency (%) 88%
84%
80%
Vo=2.8V Vo=2.0V Vo=2.5V
76% 0.0 2.0 4.0 6.0 8.0 Io (Amps) 10.0 12.0 14.0 16.0
Transient Response Vo=2.4V, Io=300mA to 15A
2.5V Linear Short circuit output response
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SC2688
POWER MANAGEMENT Outline Drawing - SO-16
Land Pattern - SO-16
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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